Three Dimensional System Integration: IC Stacking Process by Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic

By Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic

Three Dimensional method Integration: IC Stacking From approach expertise to procedure layout Edited via: Antonis Papanikolaou Dimitrios Soudris Riko Radojcic 3-dimensional (3D) built-in circuit (IC) stacking permits packing extra performance, in addition to integration of heterogeneous fabrics, units, and signs, within the similar house (volume). This leads to customer electronics (e.g., cellular, hand-held units) which may run extra strong purposes, akin to full-length video clips and 3D video games, with longer battery lifestyles. This know-how is so promising that it really is anticipated to be a mainstream know-how lower than 10-15 years from its unique perception. to accomplish this sort of finish product, adjustments within the complete production and layout means of digital structures are occurring. This ebook offers an outline of the whole trajectory from simple procedure expertise matters to the layout on the approach point of 3 dimensionally built-in nano-electronic platforms. actual layout and layout on the structure and process point are emphasised during this booklet, because the know-how has matured to the purpose that those concerns became vitally important. This e-book is meant for an viewers with a easy grab of electric engineering suggestions together with a few familiarity with fabrication of semiconductor units, Very huge Scale Integration (VLSI) and computing device structure. •Covers the complete variety of 3D chip stacking issues in one of these method non-expert (in 3D integration) reader can comprehend precisely what this expertise is, why it truly is necessary, the way it alterations traditional practices and the way it could actually impact his/her paintings; •Provides a high-level (tutorial-like) description of 3D process integration that would hide matters starting from technique know-how and production of 3D structures to the layout of 3D parts and whole structures; •First ebook to supply not just a high-level view of the complete box of 3D integration, but in addition an knowing of the interactions among some of the stages of layout and manufacturing.

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If the vertical direction is 10 mm (today, 10–12 mm is the norm for Tezzaron), then staying in the 2D plane still makes sense a lot of the time. One would not choose to go vertically 10 mm if one can instead go ­horizontally 1 mm. Thus, 3D wafer alignment is already in the correct range for most, if not all, ­applications. Certainly there will be improvements in the ­equipment and there will be applications that can drive the vertical pitch requirement lower, but today’s ­capabilities probably exceed requirements.

Rabaey J et al (2003) Digital integrated circuits, Upper Saddle River, New Jersey 07458, 2nd edn. 1 Introduction This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like materials or components – but also provides information about ­homogeneous 3D assemblies in combination with other 2D or 3D devices. One example of ­homogeneous integration is the stacking of memory layers to create a 3D memory device. In such a device, the component layers are usually made of the same ­material and are often virtually identical in design.

Because the TSVs are embedded in the field oxide, the parasitic capacitance and inductance between adjacent connections is reduced. A TSV design used in a SOI-based 3D IC technology is shown in Fig. 10. An SOI-based 3D IC technology is not the impediment it had been in the past since SOI wafer fabrication has emerged as a main line technology for high performance ICs and has also transitioned to a foundry. Fig. 10 (a) Cross-sectional and (b) isometric drawing of a TSV used in a SOI-based 3D IC technology.

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