Advanced Computing and Communication Technologies: by Ramesh K Choudhary, Jyotsna Kumar Mandal, Nitin Auluck, H A

By Ramesh K Choudhary, Jyotsna Kumar Mandal, Nitin Auluck, H A Nagarajaram

This ebook highlights a suite of top of the range peer-reviewed study papers offered on the 9th foreign convention on complicated Computing & conversation applied sciences (ICACCT-2015) held at Asia Pacific Institute of knowledge expertise, Panipat, India in the course of 27–29 November 2015. The publication discusses a large choice of business, engineering and medical purposes of the rising concepts. Researchers from academia and current their unique paintings and alternate principles, info, innovations and functions within the box of complicated Computing and conversation Technology.

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Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE J. Solid State Circuits 41(7), 1673–1679 (2006) 3. : Low-power cache design using 7T SRAM cell. IEEE Trans. -II. Express Briefs 54(4), 318–322 (2007) 4. : A novel 7T SRAM cell design for reducing leakage power and improved stability. In: International Conference on Advanced Communication Control and Computing Technologies (ICACCCT-2014), pp. 56–59. Ramanathapuram (2014) 5. , Montoye, R. : Stable SRAM cell design for the 32 nm node and beyond.

In the first approach hardware accelerator is connected to ARM CPU located on Zynq through GP interface for memory access through DMA. This brings down the performance. In the next approach accelerator is connected to ARM CPU through HP port, which increases the performance because HP ports have direct connection with DDR memory controllers on Zynq PS. In the third approach accelerator is connected through ACP port which further increases the performance because through ACP DMA can access caches of ARM cores which in turn gives low latency.

3 Power Management The SOC power issues have forced a reorganization of methodologies all over the design flow to explain power-related effects There are two types of power in SOC design one is static which is for memory and dynamic is for logic. Overall power in a chip may be dynamic power consumption, short-circuit current and leakage current will change dramatically. Increase in speed and decrease in size will lead to head dissipation and reliability issues. This may cause electro migration and IR drop for wide range of design applications.

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